1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a static random access memory (SRAM) including static memory cells.
2. Description of the Related Art
Leakage current increases in accordance with the development of microfabrication of SRAMs. A technique has been proposed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-206745, in which an increase in leakage current occurring in cell arrays is counteracted by reducing a power supply bias applied to the cell arrays in a standby state in which no write/read operations are performed.
A cell-bias control circuit comprises, for example, power-supply interruption switches for interrupting the direct application of ground potential VSS to memory cells, and clamping PMOS transistors for clamping the potential level of source potential lines isolated from the power supply. The cell bias is adjusted to an optimal value using a bias potential applied to the gate electrode of the clamping PMOS transistors.
The clamping PMOS transistors and power-supply interruption switches are arranged along ends of a cell array. Since the clamping PMOS transistors are arranged along the ends of the cell array, the bias potential line is also arranged along the ends of the cell array and is therefore long. As a result, the influence of coupling noise cannot be ignored. To avoid this influence, it is necessary to shield the bias potential line. This inevitably increases the area needed for the semiconductor device, and gives limitations on the signal lines above and below the shielded line. This problem is more conspicuous when the semiconductor device includes a plurality of arrays and accordingly includes a plurality of bias potential lines.
Further, the power-supply interruption switches are realized by, for example, NMOS transistors, which therefore are provided in a P-type well or semiconductor substrate, while the clamping PMOS transistors are formed in an N-type well or semiconductor substrate. This means that both the N- and P-type wells are necessary.
As the boundary (element isolation area) between the N- and P-type wells, a gap several times greater than that between standard wires is required. Accordingly, regardless of the size of each clamping PMOS transistor, a wide well boundary is required, resulting in an increased arrangement region of the power-supply interruption switches and the clamping PMOS transistors. Therefore, a chip size increases. Further, when the arrangement region is divided into a plurality of regions, they require a greater area.